Delta network of a cross-point switch

ABSTRACT

A switching system comprising a cross-point switch and a Delta network. The two switches are connected in parallel with common port adaptors. When a port desires a specified time reservation to another port, it sends a request message for the specified time over the Delta network to the requested adaptor at which a reservation processor grants a connection for completion at a fixed time in the future. The reservation grant is then returned via the Delta network to the requesting adaptor which, at the fixed time, sets the cross-point connection on the cross-point switch line associated with the requesting adaptor.

This .Iadd.is a reissue of Ser. No. 07/048,982 now U.S. Pat. No.4,752,777, which .Iaddend.is a continuation of application Ser. No.713,117, filed Mar. 18, 1985, now abandoned.

DESCRIPTION

1. Technical Field

The invention relates generally to multi-port switches. In particular,the invention relates to high throughput control for a wide band switch.

2. Background Art

Recent designs for high performance computers frequently involve the useof multiple devices, each operating independently, but occasionallycommunicating with one another or with memory devices when data needs tobe exchanged. For instance, there may be multiple equivalent processors,operating in parallel and each of which requires occasional access toone of multiple memory devices. Both the processors and the memories mayhave one or, at most, a small number of input/output ports for therequired data exchange to all the other processor and memories. The dataexchanges occur frequently but at random times and occur betweenseemingly random combinations of processor and memory. Some kind ofswitching network is required to connect the ports for the relativelyshort period of the data exchange.

The computer system, however, puts demanding requirements upon theswitching system. The switch must provide high bandwidth so that theprocessing is not unduly delayed while the data is being transferred.Furthermore, the connections are being frequently made and broken. As aresult, delays that occur while waiting for a connection or delaysincurred while the connection is being made can also impact the totalcapability of the parallel processors.

FIG. 1 is an illustration of one type of computer system being discussedhere. There are a large number of processors 10, each operatingindependently and in parallel with each other. In the past, it has beencommon to have the number N or parallel processors to be in theneighborhood of 4. However, newer designs involve the number Nincreasing to 256 and perhaps 1,024. Each of the processors 10occasionally requires access to one of several memories 12. For sake ofillustration, the memories will be assumed to be equivalent and also ofnumber N. Each processor 10 has an input/output path 14 and each memory12 also has an I/O path 16. The paths 14 and 16 can be buses and may beduplicated to provide full-duplex communication. The importantconsideration, however, is that the a processor 10, requiring access toa particular memory 12, requires that is I/O path 14 be connected to theI/O path 16 of the required memory 12. This selective connection isperformed by a switch 18, which is seen to be central to the design ofthe distributed processing of the computer system illustrated in FIG. 1.The use of a cross-point switch for the switch 18 provides the requiredhigh bandwidth. The important feature of a cross-point switch is that itcan simultaneously provide N connections from one side to the other,each selectively made. Although the complexity of a crosspoint switchgoes as N², the relative simplicity of the actual N² cross-points allowsits fabrication in a currently available technology. C. J. Georgiou hasdescribed in U.S. patent application, Ser. No. 544,652, filed Oct. 24,1983, now U.S. Pat. No. 4,605,928 a cross-point switch composed of anarray of smaller cross-point switches, each on a separate integratedcircuit. Although Georgiou describes a single-sided switch, as opposedto the double-sided switch of FIG. 1, Georgiou's switch can be used inthe configuration of FIG. 1 or easily adapted thereto. With thecross-point switch of Georgiou, it is easily conceivable that the numberN of ports to the switch can be increased to 1,024. Thus the totalbandwidth of the switch 18 would be 1,024 times the bandwidth of thetransmission paths 14 and 16. The cross-point of Georgiou has thefurther advantage of being non-blocking. By non-blocking is meant thatif a processor 10 requires that its I/O path 14 be connected to the I/Opath 16 of a memory 12 not currently connected, the switch 18 canprovide that connection. Thus, a processor 10 is not blocked by theswitch 18 when it requires a connection.

Georgiou has also described, in another U.S. patent application, Ser.No. 544,653, filed Oct. 24, 1983, now U.S. Pat. No. 4,630,045 acontroller for his cross-point switch. Georgiou's controller is designedto be very fast but it suffers from the deficiency of most cross-pointswitches that one controller is used for all N input ports. As a result,the controller must sequentially service multiple ports requestingconnection through the cross-point switch. Therefore, once the demandedconnection rate exceeds the speed of the controller, the throughput ofthe combined cross-point switch and the controller falls as N⁻¹. Thatis, the controller is a shared resource. Even if the controller ofGeorgiou were redesigned to provide parallel subcontrollers, perhapsattached to each port, his parallel controller would nonetheless bedepedent upon a single table, the port connection table of Georgiou'sinvention, that keeps track of available connections through the switch.Thus, the port connection table is also a shared resource and limits thecontrollers' speed for large values of N.

An alternative to the cross-point switch is the Delta network. Deltanetworks are defined, with several examples provided, by Dias et al. ina technical article entitled "Analysis and Simulation of Buffered DeltaNetworks" appearing in IEEE Transactions on Computers, Vol. C-30, No. 4,April 1981 at pp. 273-282. Patel also defines a Delta network in"Performance of Processor-Memory Interconnections for Multiprocessors",IEEE Transactions on Computers, Vol. C-30, No. 10, October 1981 at pp771-780. An example of a Delta network for packet switching is describedby Szurkowski in a technical article entitled "The Use of Multi-StageSwitching Networks in the Design of Iocal Network Packet Switching",1981 International Conference on Communications, Denver, Colo. (June14-18, 1981). The Delta network will be described here with reference tothe Omega switching network, described by Gottlieb et al. in a technicalarticle entitled "The NYU Ultracomputer--Designing and MIMD SharedMemory Parallel Computer", appearing in the IEEE Transactions onComputers, Volume C-32, No. 2, February 1983, at pages 175-189. Thisexample of a Delta network is illustrated in FIG. 2. There are eightports on the left, identified by a binary number and eight ports on theright, likewise identified by binary numbers. Connecting the right handand the left hand ports are three stages of switches 20. Each switch 20is a 2×2 switch that can selectively connect one of the two inputs onone side to one of the two outputs on the other side. It is seen thatthe illustrated Delta network can provide a connection from any port onthe right hand side to any port on the left hand side. The Delta networkis intended to be used in a parallel pipelined fashion. Data istransmitted from one side to another in relatively small packets. Thepacket contains, in addition to the data, control information, includingthe address of the desired destination. For instance, if the left-handport 000 desires to send a packet of data to the right hand port 100, itincludes the destination address 100 in the header of the packet andinputs the packet into the switch 20A. The switch 20A looks at theright-most bit of the destination address and, as a result, sends boththe destination address and the data part of the packet through its 0output to switch 20B, the switch 20B looks at the middle bit of thedestination address, a 0, and routes the package likewise through its 0output to switch 20C. The switch 20C looks at the third or left-most bitof the destination address, a 1, and thus routes the packet through its1 output to the right hand port 100. By use of buffers within theswitches 20, it is possible to decouple the switches of the differentsections so that the control and transmission are pipelined between thestages of the 2×2 switches 20. Thus the control function of the Deltanetwork is potentially very fast and the delay introduced by the stagesrises as log N rather than the N dependence of the cross-point switch.It is seen that the Delta network of FIG. 2 can provide paralleltransmission paths, thus increasing the bandwidth of the system.However, the Delta network is a blocking network, that is, there is noguarantee that a connection path is available through a switch even ifthe desired output port is otherwise available. For instance, if thepreviously described connection between the 000 port on the left-handside and the 100 port on the right-hand side is made, the left-hand port001 is blocked from reaching the four right-hand ports 000, 010, 100 and110. The previously described connections would need to be broken beforethe blocking is removed. Thus, a Delta network is potentially fast, butas traffic increases, blocking delays can be expected.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide a cross-pointswitch with high bandwidth.

It is a further object of this invention to provide a cross-point switchthat is non-blocking for data transmission.

It is yet a further object of this invention to provide a cross-pointswitch for which the control functions do not severely slow for a largenumber of input and output ports.

The invention can be described as a switching system in which across-point switch provides high bandwidth, non-block connections fordata transmission. Multiple controllers are provided at either the inputor output ports for controlling the cross-point connections to thatport. There is further provided a Delat network between the input andoutput ports that allow a pipelined switching of control information toor from the controllers. An access request to a port is granted on areservation basis. That is, a control request is made over the Deltanetwork requesting a fixed block of connection time. The controllerreceives these requests and sets up a schedule for connection andperhaps transmits back over the Delta network to the requesting port thetime delay before its time connection will be honored.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a general illustration of a multi-port switching system.

FIG. 2 is a schematic illustration of a Delta network.

FIG. 3 is a schematic representation of the overall design for theswitching network of the present invention.

FIG. 4 is a time diagram illustrating the propagation of control messagethrough the Delta network.

FIG. 5 is a schematic representation of a 16×16 Delta network.

FIG. 6 is a schematic diagram of a switching node of the Delta networkof the present invention.

FIG. 7 is a more detailed schematic diagram of the forward directioncomponents of the switching node of FIG. 6.

FIG. 8 is a detail schematic diagram of an alternate embodiment for theforward output buffer of a node.

FIG. 9 is an illustration of the memory organization of the outputbuffer of FIG. 8.

FIG. 10 is a schematic diagram of the forward path control of FIG. 7 andits associated components.

FIG. 11 is an illustration of the memory organization for an alternateembodiment of the combined request buffer and list register of FIG. 7.

FIG. 12 is a schematic diagram of the reservation processor.

FIG. 13 is a schematic diagram of the return direction components of theswitching node of FIG. 6.

FIG. 14 is a connection diagram for a full-duplex crosspoint switchusable with this invention.

FIG. 15 is a alternate embodiment for the circuit of FIG. 14.

FIG. 16 is an illustration of a perfect shuffle network.

FIG. 17 is a timing diagram illustrating a multiplexed operation of analternate embodiment of this invention.

FIG. 18 is a block diagram of a multiplexed embodiment of the invention.

FIG. 19 is a timing diagram for a hierarchical method for sendingcontrol messages.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

This invention combines the best features of a cross-point switch and aDelta switching network by providing a non-blocking cross-point switchfor data transmission and by additionally providing a Delta networkswitch for switching control information between the input and outputports of the cross-point switch. Parallel controllers of the cross-pointswitch are provided at each port of one of the sets of ports of thecross-point switch. FIG. 3 illustrates one embodiment of the inventionwhen there are four input ports, I₀ -I₃, and four output ports, O₀ -O₃,that is, N=4. Each input port is connected to a respective input adaptor30 and each output port is connected to an output adaptor 32. Across-point switch 34 has four horizontal lines 36 connected to theinput adaptors 30 and four vertical lines 38 connected to the outputadaptors 32. At each intersection of a horizontal line 36 and a verticalline 38 is a cross-point that is individually selectable to make theconnection between the respective horizontal line 36 and vertical line38. A cross-point controller 40 is associated with each horizontal line36 to control the cross-points of that horizontal line 36. Thisembodiment thus is horizontally partitioned because the controllers areassociated with the input ports rather than the output ports. Eachcross-point controller 40 is itself controlled by associated inputadaptor 30.

The cross-point switch 34 is used primarily for the selectivetransmission of data while a separate Delta network 42 is used primarilyfor the selective transmission of control information between the inputadaptors 30 and the output adaptors 32. For N=4, two stages, each withtwo 2×2, switches 44 are required. The Delta network differs from thatof FIG. 2 because each switch 44 has its own buffering and the adaptors30 and 32 also require buffering. The embodiment of FIG. 3 is presentedfor illustrative purposes and it is anticipated that the invention willbe used primarily for considerably larger values of N, for example, 512or 1024. For the more realistic embodiments, difficult to illustratehere, there would be additional stages of the 2×2 switches 44 and it isprobable that the 2×2 switches 44 would be replaced by 4×4 switches or8×8 switches. However, the basic configuration of the memory systemwould remain the same.

In some situations, it may be preferable to have the Delta network 42 toconsist of three stages of four switches 44 in each stage. Theright-most and left-most stage would consist of 1×2 switches. In thisdesign, the buffering for the adaptors 30 and 32 can be performed by the1×2 switches.

The fundamental problem in controlling a cross-point switch is toascertain whether the desired resources are available, in this case, therequired horizontal line 36 and vertical line 38 of the cross-pointswitch 34. The controller 40 of the horizontally-partitioned cross-pointswitch is easily able to decide if its associated horizontal line 36 isavailable. A much more difficult problem is for the controller 40 toknow if the desired vertical line 38 is available or whether anothercontroller 40 has connected a different cross-point to the desiredvertical line 38. The Delta network 42 provides the fast and efficientmeans of obtaining this information.

When an input adaptor 30 receives a request from its input port I₀ -I₃for a connection to a designated output port O₀ -O₃, the input adaptor30 directs this request through the Delta network 42 to the designatedoutput adaptor 32. The adaptor 32 keeps a record of the use of itsassociated vertical line 38.

The request that the input adaptor 30 transmits to the output adaptor isin the form of a control message S^(C) _(ij) where i is the number ofthe input adaptor 30 and j is the number of the output adaptor 32 thatis being requested. The form of the control message is S^(C) _(ij)=(A_(i),A_(j),T,C). The first two parameters are the addresses or thenumerical designations of the input adaptor 30 and the output adaptor 32respectively. The second parameter T in the original request is thelength of time that the i-th input adaptor 30 is requesting forconnection to the j-th output adaptor 32. The third field C is a controlfield and may contain information such as the requested address tomemory and whether the requested connection is for a read or writeoperation. The destination address A_(j) is used for routing the controlmessage S^(C) _(ij) through the Delta network 42 to the designatedoutput adaptor 32. The source address A_(i) is used for routing a replyto that request back to the input adaptor 30 through the same Deltanetwork 42.

As is described in the previously cited technical article by Gottlieb etal, it is possible to combine the fields of the source and destinationaddresses into a single field A. When the control message leaves theinput adaptor 30, the address field A contains the destination addressA_(j). As the control message is switched through the Delta network 42,the switches 44 and 44 know on which input port to the respective switchthe control message arrived. The number of the input port is one bit ofthe address of the requesting input adaptor 30. As a result, the switch44 or 44 can replace one of the bits of the destination address A_(j)with the number of the input port used with that switch. Thus, after thecontrol message has traversed the Delta network 42 toward the outputadaptor 32, the address field A contains the source address A_(i). Aswill be explained later, it may be necessary to include an extra bit inthe combined address field A. Of course, the combined field A provides ashorter control message, thus reducing the probability of a blocked nodein the Delta network 42.

FIG. 4 is a time history that shows on the left the time required forthe control message to be transmitted from the input adaptor 30 throughthe Delta network 42 to the output adaptor 32. This propagation time mayinvolve delays at one or more switches 44 because the node is blocked.Each output adaptor 32 has a time register or reservation clock thatshows the time t_(oc) at which the output adaptor 32 will have completedprocessing all connection requests in its reservation queue. This timet_(oc) is thus the time at which a new request can be honored. When theoutput adaptor 32 receives the control message S^(C) _(ij) (A,T,C), itreplaces the time field T in the control message by the reservation timeV that is equal to t_(oc) and increments the reservation clock by T. Itis seen that the series of operations by the output adaptor 32 can beperformed by the fetch-and-add operation described by Gottlieb. However,V is never allowed to have a value lower than t_(min) where t_(min) isthe propagation time from the output adaptor 32 back to the inputadaptor 30, assuming that there are minimal blocking delays within theDelta network 42. In this case, t_(oc) is incremented by t_(min) +T.

The control message sent back to the input adaptor 30 is S^(R) _(ij)(A,V). When the returned control message S^(R) is received by theoriginating input adaptor 30, that adaptor knows the time V at which itcan initiate the sending of the message to the respective outputadaptor. When that time V arrives, the input adaptor 30 instructs itsassociated controller 40 to make the cross-point connection (ij) in thecross-point switch 34 and the input adaptor 30 then proceeds to send itsmessage. At the same time, the output adaptor 32 has prepared itself toreceive the message designated by the senior member of the reservationqueue.

If the return control message was unduly delayed in the Delta network42, the reservation time V may have already passed. If the reservationtime V received by the input adaptor 30 has passed, as compared to thesystem clock, part of the reserved time has already expired at theoutput adaptor 32. Accordingly, it is impossible to transmit the entiredesired message and the input adaptor 30 must make another request forthe same data message.

It is seen that the cross-point controllers 40 are associated with theinput ports and guarantee against a double use of the horizontal line36. The output adaptors 32 guarantee, by means of the reservation,against a double use of the vertical lines 38.

Description of the previous embodiment is adequate for an understandingof the concept of the basic invention. However, it lacks detail as tothe hardware necessary for an efficient Delta network. Furthermore, theefficiency of the Delta network can be a greatly increased in heavytraffic situations if control messages can be combined within the DeltaNetwork when two or more input ports ports are sending control messagesto the same output port. There is a high probability at any one timethat one of the output ports is receiving a large number of controlmessages, at a faster rate than what it can handle. In such a situation,the node immediately associated with that output port must inhibit allother nodes connected to it from sending further control messages. Ifthe buffering capabilities of the intermediate nodes are exceeded, theinhibition extends through a major part of the Delta network, thusblocking the transmission of control messages to other output ports.Thus, significant buffering should be provided at each of the nodes ofthe Delta network. Furthermore, to further limit blocking by a heavilyused output port, it is advantageous to combine messages within theDelta network such that the output port needs only act upon a simplecombined message and the decombining of the return control message isperformed at the intermediate nodes of the Delta network which areoperating in parallel and which do not have such an extended inhibitingeffect in a blocking situation.

FIG. 5 shows in 16×16 Delta network 50 connected to 16 input adaptors onthe left-hand side and 16 output adaptors on the right-hand side. TheDelta network 50 comprises four stages of nodes or switches 52, eachstage identified by a depth from the input adaptors. The nodes are all2×2 switches. The outputs of the nodes of depth 3 are connected torespective output adaptors through reservation processors 54, to bedescribed later. The nodes 52 are arranged in rows and numbered from 000to 111 according to the higher order bits of the input lines and aparticular node can be identified by its row and its depth. For example,node 011(2) is in row 011 at a depth of 2.

The i-th input adaptor sends the control message S^(C) _(ij) to thereservation processor 54 associated with the j-th output adaptor whereS^(C) _(ij) =(A,C,T,D,α,K). The three added parameters, D, α and K, arerequired for the combining function. The first parameter A is thecombined address field, previously described except for the inclusion ofan extra bit. For example, a message from input adaptor 0001 intendedfor an output adaptor 0001 enters node 001(1) from input adaptor 0001with an address of x0001. The extra left-hand bit is set to 1, i.e.,10001, by node 001(1) to indicate the input port from which it came.Note that after leaving node 000(1) only the three right-hand bitsdetermine the subsequent path in the forward direction through the Deltanetwork 50. The process is repeated until the message leaves node 000(3)for output adaptor 0001 at which point A=1000y. The address 1000 is theaddress of the input adaptor 0001 written in reverse order and the extrabit y is on the right.

The second parameter C contains control information, as describedpreviously. For example, the control information might include theidentifier of a line to be read from storage memory connected to theoutput adaptor. If the storage has 32 bit addresses (a typical situationin a main frame computer) and 128 byte lines, the storage would require22 bits of addressing information in the control information C in orderto identify the line. In addition to the line address, the controlinformation C would include the type of operation to be performed, e.g.,read or write. The inclusion of this operational information in thecontrol message allows the accessing delays to the storage to overlapthe delays introduced by the cross-point switch and the Delta network50. This control information including an address is particularly usefulwhen data is being accessed from a bulk memory on the destination sidethat is combined with a cache. The addressing information in the controlmessage allows the data to be transferred or pre-fetched from bulkmemory to the cache prior to the actual data access through thecross-point switch. For instance the address would be a line address for128 bytes of data.

The control information C further contains an indicator as to whetherthe original control information was left behind in a message combiningoperation or, alternatively, an identifier of a message which wascombined into a combined message that has the highest priority and thusretains the associated addressing information. The parameter T is thetime required for the operation if there is no provision for overlappingof accessing delays and switching delays. In the simplest case, theconnecting time T that is originally requested would be a single unit.e.g., the unit required to read one line of a memory. However, theparameter T could be increased if messages are combined at theintermediate node.

The remaining parameters, D, α and K, in the forward control messageS^(C) _(ij) are required for the combining operations at the nodes. Theparameter D is one plus the depth within the Delta network 50 at whichthe most recent combining operation occurred. For example, D=3 ifcontrol messages were combined at node 110(2). Initially, D=0, i.e., nocombining has yet been performed. This information is included so that,on the reply in the backward direction through the Delta network 50, aquick determination can be made as to whether the decombining needs tobe performed. The parameter α is an identifier, inserted by a combiningnode, to identify for its own use the combining operation that producedthe combined message. The combining nodes associate the identifier αwith control messages retained in its own buffer. The parameter K is thenumber of nodes at which combining was done for a given message. When acontrol message has been combined, a reply message in the oppositedirection must be decombined, thus producing a delay in the backwardpath. The parameter K is a measure for the delay for the highestpriority message on the return path and serves to determine the earliestreservation time which could be used. Initially, K is set at zero.

Each node of the Delta network 50 has a structure schematicallyrepresented in FIG. 6. Control data is received in the forward directionon two forward data input paths 60 and 62 from the previous stage ofnodes. The forward control data is received, controlled, possiblybuffered and then switched to one of two forward output data paths 64and 66. These functions are controlled by a forward direction controland buffering circuit 68 to be described in detail later. The forwarddata output paths are connected to the next stage in the Delta network60. This structure is generally duplicated for control messages sent inthe return direction by return data input paths 70 and 72 and returndata output paths 74 and 76 connected by a return direction control andbuffering circuit 78.

Each of the data paths 60 and 66 and 70-76 has an associated inhibitline going in the reverse direction to or from the same node in theneighboring stage. Whenever a control and buffering circuit 68 or 78 hasfilled its output buffers so that no more messages can currently behandled, it puts an active signal on both of its output inhibit lines 80and 82 or 88 or 90. This inhibition indicates to both of the neighboringnodes on one side, which are possibly transmitting to that circuit 68 or78, that no more messages should be transmitted. Thus when the forwarddirection control and buffering circuits 68 detects an active signal oninhibit line 84, it will not transmit control messages on the associateddata paths 64. Likewise, when the return direction and control bufferingcircuit 78 detects an active inhibit signal on line 92, it will nottransmit a return control message on the associated data path 74.

A combined request buffer 96 is accessible by both the forward andreverse direction control and buffering circuits 68 and 78 for thestorage and subsequent retrieval of combined messages. A fullnessregister 98 keeps track of the number of messages currently being storedin the combined request buffer 96. The fullness register 98 isincremented by the forward direction control and buffering circuit 68when it stores a message in the combined request buffer 96 and thereturn direction control and buffering circuit 78 decrements thefullness register 98 when it retrieves a message from the combinedrequest buffer 96. The messages stored in the combined request buffer 96are indexed by an identifier provided by the forward direction controland buffering circuit 68. There are only a finite number of allowedidentifiers and the list register 100 keeps track of which identifiersare in use. If there are only 8 allowed identifiers, then the listregister 100 could be an 8-bit register. The forward direction controland buffering circuit 68 would set the bit corresponding to anidentifier indicating that it is being used for messages being stored inthe combined request buffer 96. When the return direction control andbuffering circuit 78 retrieves the last identified message from thecombined request buffer 96, it resets the corresponding bit in the listregister 100 to indicate that that identifier is now available.

The forward direction control and buffering circuit 68 is shown in moredetail in FIG. 7. Input buffers 110 and 112 are connected to the forwardinput data paths 60 and 62 and are of sufficient size to contain onecontrol message S^(C) _(ij) apiece. The input buffers 110 and 112 have afurther function of modifying the address in the combined address fieldA. This can be easily accomplished by tying the output of the addressbit to be modified to a zero value for the input buffer 110 and to a onevalue for the input buffer 112, regardless of the value of that bitinput to the input buffer 110 or 112. For instance, in the previouslydescribed example for the 000(1) node, the left-most address bit isalways output as a 1 from the input buffer 112.

A path control circuit 114 controls the routing of messages between theinput buffers 110 and 112 and the forward output data paths 64 and 66 aswell as the routing to and from an output buffer 116 controlled by abuffer and combination controller 118. Associated with the output bufferis a fullness register 120 which indicates the number of messages storedin the output buffer for transmission on the forward output data paths64 and 66. When a message is received at the input buffer 110 or 112,the path control circuit reads the single bit of the address fieldindicating the direction of switching. At depth d, the message isintended for the forward data output path 64 if the bit a_(d+1) =0 andis intended for the data path 66 if a_(d+1) =1. The path control circuit114 immediately forwards a message from the input buffer 110 or 112 toits indicated output path 64 or 66 if the output buffer 116 is empty, asindicated by the fullness register 120 and if the path 64 or 66 isavailable.

The path 64 or 66 is available if two conditions are satisfied. Theinhibit line 84 or 86 associated with the output data path 64 or 66 mustbe off. Furthermore, the message in the input buffer 110 or 112 must bethe only message in the input buffers 110 and 112 for the indicatedpath. That is, the other input buffer must either be empty or contain amessage directed to the other output path. If, however, both inputbuffers 110 and 112 contain messages directed to the same output path 64or 66, there is a conflict or contention for that output path. Onemethod of solving the contention is to proceed with the combiningoperation to be described later. However, in order to minimizeforwarding delays in the light traffic situation when the output bufferis empty, it is recommended that the contention be immediately resolvedby the path control circuit 114. In the preferred resolution method, thepath control 114 keeps track of which of the input buffers 110 and 112has last forwarded a message to the output path 64 or 66. The inputbuffer 110 or 112 which was not the last to forward is given priority inthe contention and its message is forwarded before the other. That is,the path control circuit 114 causes priority to alternate between theinput buffers 110 and 112.

The output buffer 116 stores messages waiting to be forwarded on theoutput data paths 64 and 66. The output buffer 116 must be contentaddressable both for the remaining destination address part of thecombined address field A, to be used in the combining process, and forthe two addresses of the two output data paths 64 and 66. Furthermore,the output buffer 116 must operate as a first-in/first-out buffer forall of its contents addressed respectively to the two output data paths64 and 66. These functions can be easily performed by dividing theoutput buffer 116 into two outpout buffers 116a and 116b, as shown inFIG. 8. Each of the output buffers 116a and 116b is dedicated torespective output data lines 64 and 66. Fullness registers 98a and 98bare associated with the respective divided output buffers 116a and 116b.Associated with each output buffer 116a or 116b is an H register 122a or122b and a T register 124a or 124b. The H and T registers are used forpointers to control the first-in/first-out buffering function. Thememory organization of an output buffer 116a or 116b is shown in FIG. 9.The buffer 116a or 116b consists of n+1 addressable storage locations,each storing one control message S^(C) _(ij). The T register 124a or124b points to the next storage location in the output buffer 116a or116b in which a message is to be stored. The H register 122a or 122bpoints to the oldest stored messages which will be the next message tobe retrieved. FIG. 9 illustrates 3 storage locations for 3 messagescurrently being stored in the buffer. When another message is stored inthe output buffer 116a or 116b, the T register is decremented by 1.Likewise, when a message is retrieved, the H register 122a or 122b isdecremented by 1. When either H or T is equal to 0, a further decrementwill produce a value of n for that pointer H or T, that is, the pointerswrap around. It is to be noted that when H=T after a message has beenstored, then the associated output buffer 116a or 116b is full. However,when H=T after a message has been retrieved, then the associated bufferis empty.

A more detailed schematic showing the circuitry associated with the pathcontrol circuit 114 is illustrated in FIG. 10. Associated with each ofthe two input buffers 110 and 112 is a buffer status register 130 or 132that contains two bits of information (b₁,b₂). The value of the firstbit is b₁ =1 if there is a message waiting in the associated inputbuffer 110 or 112. The second bit b₂ is taken from the bit of theaddress field A that is being used in this stage of the Delta network.That is, the second bit is b₂ =0 if the control message is to switchedto the output data path 64 and b₂ =1 if it is to be switched to theoutput data path 66. Two additional registers 134 and 136 are associatedwith each of the output data lines 64 and 66 and indicate the source ofthe last message transmitted on that line. That is, the contents of thelast message register 134 associated with the data output lines 64 isset to 0 if the last message transmitted on line 64 was received fromdata input line 60 and is set to 1 if the messages was received on datainput line 62. The path control circuit 114 increments the fullnessregister 120a when a message intended to be transmitted on the outputdata line 64 is buffered in the output buffer 116a. When the bufferedmessage is retrieved from the output buffer 116a and transmitted on thedata output line 64, the path control circuit 114 decrements thefullness register 120a. Similar incrementing and decrementing isperformed upon the fullness register 120b as messages are buffered inthe output buffer 116b for transmission on the data output line 66.

The forwarding of messages onto the top data output line 64 will now bedescribed. A similar explanation would, of course, apply to the bottomdata output line 66. At most one control message is transmitted on theupper data output line 64 per control cycle. A message select flag isset when a message to be transmitted on this line has been selected. Ifno message has been selected, then the message select flag is reset. Ifthe inhibit line 84 associated with the data output line 64 is active,then no messages can be transmitted. If the contents of the bufferstatus register 130 or 132 is detected to be (b₁,b₂)=(1,0), then thepath control circuit recognizes that a message has been received fortransmission on an inhibited data output line. Instead, the path controlcircuit 114 forward the message from the respective input buffer 110 or112 to the buffer and combination controller 118 for storage orcombining.

If, however, the inhibit line 84 is not active, the fullness register120a is interrogated through the buffering and combination controller118 to determine if it contains a non-zero value, that is, that here aremessages waiting in the output buffer 116a. If the fullness register120a is greater than 0, then the next message the output buffer 116 isretrieved and the fullness register 120 is decremented. The last messageregister 134 is then updated according to the origin of this message andthe message select flag is set.

If the output buffer 116a does not having waiting messages, indicated byan empty fullness register 120a, then messages in the input buffers 110and 112 can possibly be immediately forwarded. A message in the inputbuffer 110 is immediately forwarded to the data output line 64 ifeither: (1) the last message register 134 is 0 and the contents of thebuffer status register 130 are (1,0) or (2) the content of the lastmessage register 134 is a 1, the upper buffer status register 130contains (1,0) and the first bit b₁ of the lower buffer status register132 is 0. Similarly, a message is transmitted from the lower inputbuffer 112 if either: (1) the content of the last message register 134is 1 and the contents of the lower buffer status register 132 are (1,0),or (2) the last message register 134 is 0, the lower buffer statusregister 132 is (1,0) and the first bit b₁ of the upper buffer statusregister 130 is 0. If a message is to be sent under any of theseconditions, then the message select flag is set. If however, either theupper or lower input buffers 110 or 112 have an incoming message whichcannot be immediately forwarded because none of the above conditions aresatisfied, then the message is forwarded to the buffer and combiantioncontroller 118.

The operation of the buffer and combination controller 118 will now bedescribed as it buffers and possibly combines a message. The controller118 receives a control message S^(C) (A,C,T,D,α,K) from the path control114. It is assumed that the node 52 is a depth of d. The controller 118takes the remaining bits of the combined address field A that designatethe destination address, that is, a_(d+1), a_(d+2) . . . and comparesthem with the corresponding bits of messages already stored in theoutput buffer 116. That is, the output buffer 116 is content addressableaccording to the field a_(d+1), a_(d+2) . . . . Since in the preferredimplementation the output buffer comprises two output buffers 116a and166b associated with the two output data paths 64 and 66, the first bita_(d+1) points to one or the other of these two output buffers 116a and116b. These two buffers 116a and 116b are then individually contentaddressable to the remaining address bit or bits a_(d+2), a_(d+3) . . .. However, the two output buffers 116a and 116b are content addressableonly between their respective T and H pointers for the valid messagescurrently stored therein. If no message is found with the correct bits,then the currently received control message is stored at the locationpointed to by the T register 124a or 124b as the message M_(i)=(A,C,T,D,α,K). The T register 124a or 124b is decremented and theassociated fullness register 120a or 120b is incremented. This completesthe buffering operation and no message combining was performed.

If, however, a message was found with the correct address bits, it willhave the form M_(i) =(A_(i), C_(i),T_(i),D_(i),α_(i),K_(i)). It was theproper bits of the address A_(i) that matched the corresponding bits ofthe address A. If the depth parameter of the stored message equals thedepth of the node 52, that is, D_(i) =d, then the message M_(i) hasalready been combined at this level. The combining process in this case,involves increasing the time parameters T_(i) of the already storedmessage M_(i) by the time parameter of the newly arrived message S^(C),that is, M_(i) = (A_(i),C_(i),T_(i) +T, D_(i),α_(i),K_(i)) for the newlycombined stored message. The incremented time parameter is the totaltime required to service all the tasks of all the combined controlmessages. When a control message S^(C) is combined with an alreadycombined message M_(i), then a truncated version of the control messageS^(C) is stored in the combined request buffer 96 as a cataloguedmessage M*=(A,T,D,α;α_(i)). In the present embodiment, the controlmessage parameters C and K are not required when the messages aredecombined so are not stored with the catalogued message M*. The lastparameter α_(i) has been taken from the already combined message M_(i)and is one of the identifiers used to identify which catalogued messagesM* are associated with a single combined message M_(i) as well as toidentify the message that will eventually be returned from thereservation processors 54.

Of course, whenever a catalogued message M* is stored in the combinedrequest buffer 96, the buffer and combination controller 118 incrementsthe associated fullness register 98. Once the control message S^(C) hasbeen combined into the buffered message M_(i) and its associatedcatalogued message M* has been stored, the buffer and combinationcontroller 118 is ready for the next cycle.

If the message M_(i) found in the output buffer 116 has a depthparameter D_(i) less than d, then the aleady buffered message M_(i) hasnot previously been combined at this depth d. In this case, thecontroller 118 creates a newly combined message from S^(C) and M_(i) ofthe form M_(i) =(A.sub. i,C_(i),T_(i) +T,D,α',K_(i) +1). The identifierα' is a new identifier that is indicated as being currently unused inthe list register 100. The list register 100 is then changed to indicatethat the identifier α' is now in use. If no further identifiers areavailable, the inhibit lines 80 and 82 are set active to prevent thereception of further messages. For a newly combined message, twocatalogued messages are stored in the combined request buffer 96 of theform M_(i) *=(A_(i),T_(i),D_(i),α_(i) ;α') and M₂ *=(A,T,D,α;α'). Thatis, both the control message S^(C) and the already stored message M_(i)have associated catalogued messages that are stored, both of which arecatalogued by the same identifier α'. This double stored requires thatthe fullness register 98 be incremented by 2. Whenever the fullnessregister 98 indicates that there is less than two slots unfilled in thecombined request buffer 96, then the buffer and combination controller118 causes the inhibit lines 80 and 82 to go active to prevent thefurther reception of messages that could perhaps cause the combinedrequest buffer 96 to overflow.

It should be noted at this time that the choice of the parameters A_(i),C_(i) and K_(i) for inclusion in the newly combined message M_(i) wasarbitrarily selected from the already stored but never combined messageM_(i). These parameters could equally well have been taken from thecontrol message S^(C). It is possible to set up a priority scheme in thecontrol parameter C such that the message with the highest priorityalways retains its parameters upon combining. This is particularlyuseful when the control parameter C is being used as addressinginformation at the destination port. Of course, only one such set ofaddressing information can be transmitted in the control field C_(i) ina combined message M_(i).

It is preferred in the combining process that a message in the outputbuffer 116a or 116b not be involved in a combining operation if thatmessage is already at the top of the queue. An attempt to combine thesenior member of the queue is likely to result in a delay in thetransmission of messages from the buffer. Accordingly, referring to FIG.9, only those message located at or between the locations T+1 and H-1are content addressable for the address bits a_(d+1), a_(d+2), . . . .

The memory organization for the combined request buffer can beadvantageously integrated with that of the list register 100 so as tocompletely utilize the available buffering capacity. A list register100' contains one location for each of the identifiers α. A usage bitindicates whether the associated identifier α is currently in use. Theidentifier itself needs not be stored but can simply be the address ofthe location. A length parameter indicates the number of cataloguedmessages in a combined request buffer 96' that are catalogued by theidentifier α. Finally, for every identifier α, there is a pointer to alocation of one of the catalogued messages in the combined requestbuffer 96'. The combined request buffer 96' is another memory havingmultiple locations. An occupancy bit indicates whether a location ispresently being used for storage of a catalogued memory M*. The locationfurther contains a pointer to another location in the combined requestbuffer 96' for another message associated with the identifier α. Thecombined request buffer 96' can store catalogued messages M* for anycombination of identifiers α in any combination of storage locations.The combined request buffer 96' is thus addressable by the identifier αwhich points to one of a series of catalogued messages. Whenever anothercatalogue message is stored in the combined request buffer 96' thestring of pointers is traced to the last catalogued message, M₃ * in theillustrated example. Then the occupancy bits of other locations aretested to see if those locations are available. When an availablelocation is found, that address is then inserted into the pointer fieldof the location of the last catalogued message, the new cataloguedmessage is stored in the pointed-location, the occupancy bit is changedto one and the length parameter in the list register 100 is incrementedby one. It should be noted that in this scheme the second identifier α'in the catalogued message M* is redundant since this information isavailable from the string of pointers.

An alternate approach for setting and resetting the inhibit lines 80 and82 will be described later.

With the structure for the nodes 52 as described above, control messagesS^(C) can either be immediately be forwarded from one node to anothernode at a different depth, the control message can be transmitted inuncombined form after temporary storage in the output buffer 116a or116b, or a combined message can be transmitted from the output buffer116a or 116b. Furthermore, control messages may be combined at differentdepths with corresponding catalogued message M* being left behind at thecombined request buffer 96 at the various depths of combining.

The control message S^(C) is eventually received at the reservationprocessor 54, illustrated in FIG. 12. It is immaterial to thereservation processor 54 if the control message S^(C) is a combinedmessage or an uncombined message. They are both treated the same. Thereceived control message S^(C) is stored in an input buffer 130. Theaddress field A, the depth parameter D and the identifier α of thecontrol message S^(C) are immediately forwarded to an output buffer 132for inclusion in the return message S^(R). The control information C isforwarded to the output adaptor 32. If the output adaptor 32 has a cachememory and the control information C contains the address for the pageof memory required from the bulk memory associated with the outputadaptor 32, then the page can be pre-fetched into the cache memory alongwith its memory address for quick access when the connection through thecross-point switch 34 is finally completed.

A reservation processor unit 134 receives the time parameter T and thenumber of combining levels K from the input buffer 130.

The time T is the total time being requested, possibly for a number ofcombined messages. On the other hand, the number of combining levels Kis associated with only one of the uncombined messages in the controlmessage S^(C). A system clock provides a real time signal t to thereservation processor unit 134. A register 136 contains the absolutetime t_(oc) for the beginning of the first available reservation. Thistime t_(oc) is set by the reservation processor unit 134 but is alwaysequal to or greater than the system clock time t. This function can beeasily implemented by a comparison circuit.

The purpose of the reservation processor 134 is to calculate an absolutereservation time V for transmission back through the Delta network andfor calculating new values of the available reservation time t_(oc). Thefunctional dependence of these two parameters depends upon anotherparameter Δ=(t+ t_(min) +ZK)- t_(oc). The parameter t is the value ofthe system clock and t_(oc) is the current value in the register 136.The parameter t_(min) is a parameter of the system and represents thetime required for the return message S^(R) to traverse the Delta network42 back to the input adaptor 30. This parameter is for the case wherethere has been no combining, and hence no decombining is required forthe return message, and further assumes that there is no blockage at thenodes 52 for the return message. The parameter Z is the expectedadditional decombining delay for decombining at one node 52. Thus theproduct ZK is the total decombining delay expected for the one originalmessage that has provided the levels of combining K and the controlinformation C. Then the sum of t+t_(min) +ZK is the expected time ofarrival of the return message S^(R) at the one input adaptor 30 thatoriginated the one control message with which K and C are associated. Ifthe expected time of arrival is later than the available reservationtime t_(oc), that is, Δ greater than 0, then the available reservationtime t_(oc) is too early to be usable and Δ represents a time that willbe wasted until connection can be made. In this case, the time Vtransmitted the return message is set to V=t_(oc) +Δ which is the abovementioned arrival time at the input adaptor 30. In this case also, theavailable reservation time register 136 is incremented by the wastedtime value Δ and the requested reservation time T. The new value of theavailable reservation time t_(oc) is thus the time following theprocessing of all the tasks associated with the control message S^(C).

If, however, the value of Δ is less than or equal to 0, then there is nowasted time Δ. The time parameter V returned in return message S^(R) isset to the current value t_(oc) of the available reservation timeregister 136 and this register is then updated by the reservation timerequest T. Once the output buffer 132 has received the values of A, D, αand V, the return message S^(R) (A,V,D,α) is returned to the Deltanetwork 50 for transmission in the reverse direction.

The propagation of the return control message SR through the DELTAnetwork 52 is very similar to the propagation of the forward controlmessage S^(C) through this same network. The return direction controland buffering circuit 78, illustrated in FIG. 13 is very similar to thatof the forward direction control and buffering circuit 68 of FIG. 7. Theswitching between the return input data lines 70 and 72 and the returnoutput data lines 74 and 76 is performed according to one bit of thecombined address field A in the return message S^(R). As mentionedpreviously, in the switching in the return direction, the bits in thecombined address field are read from right to left. The returnedmessages are buffered in input buffers 140 and 142. A return pathcontrol circuit 144 controls the switching of return messages S^(R)through the switch. An output buffer 146 is similar to the output buffer116 except that it does not need to be content addressable but operatesstrictly as a first-in/ first-out buffer. A fullness register 147maintains a count of available slots in the output buffer 146. Theoutput buffer 146 and 147 may be implemented as dual buffers andregister, as shown in FIG. 8.

If the output buffer 146 has messages waiting to be transmitted, thepath control circuit 144 receives those messages through a buffer anddecombination controller 148 for transmission on the return data outputlines 74 and 76 according to the proper bit in the address field A. Forevery message taken from the output buffer 146, an associated fullnessregister 148 is decremented. If the fullness register 148 is decrementedwhen the inhibit lines 88 and 90 are active, the inhibition is removed.Just as in the case of the forward switching, the return messages aretransmitted only when the required data output line 74 or 76 isavailable. If the output buffer 146 is empty, as indicated by itsassociated fullness register 148 then a message in the input buffer 140or 142 is transmitted to the proper data output line 74 or 76 if thatline is available and if the depth parameter D in the return messageS^(R) (A,V,D,α) does not indicate that decombining is required at thisdepth, that is, if D does not equals d. If the return message S^(R)cannot be forwarded immediately, then it is sent to the buffer anddecombination controller 148.

The controller 148, upon receiving a return message from the pathcontrol circuit 144, stores that message in the output buffer 146 if Ddoes not equal d. It then also increments the fullness register 148.When the fullness register 148 indicates that the output buffer 146 isfull, the inhibit lines 88 and 90 are set active to inhibit thetransmission of further return messages.

If the depth parameter D equals d in the control message received by thecontroller 148, then this return message must be decombined at thislevel. The return message is of the form S^(R) =(A,V,d,α). The combinedrequest buffer 96 will have at least two catalogued messages M_(i)*=(A_(i),T_(i),D_(i),α_(i) ;α). The content addressability is madeaccording to the identifier α. These catalogued messages are taken outof the output buffer 146 in first-in/first-out order and are insertedinto the output buffer 146 as multiple return messages of the form atS^(R) =(A_(i),V_(i),D_(i),α_(i)) for the requisite sequence of ibeginning at 1. The adjusted reservation time V_(i) is sequentiallycalculated for the number of catalogued messages, namely, V₁ =V andV_(i+1) =V_(i) +T_(i). The effect is to allocate the reservation time Vin the combined return message S^(R) to the various decombined messages.Of course, as messages are decombined and put into the output buffer116, the fullness register 120 must be properly incremented and thetransferring must be stopped when it indicates that the output buffer116 is full. In this case, the inhibit lines 88 and 90 are activated.

In this way, any combined return messages S^(R) are decombined at thesame lever and node at which the control message S^(C) producing themhad been combined. Furthermore, a single return message may bedecombined at more than one depth if the depth parameter D in thecatalogue message M* indicates the further need of decombining. In thisway, return messages arrive back at the input adaptors 30 as single,uncombined return messages. The input adaptor 30 then uses thereservation time V contained in the return message S^(R) as the time tocause the associated controller 40 to make the required cross-pointconnection in the cross-point switch 34. If, because of blockage on thereturn path or for other reasons, the reservation time V returned to aninput adaptor 30 is earlier than the time at which it is received atthat adaptor 30, no connection is made and the connection request mustbe resubmitted. At the end of the originally requested connection timeT, the controller 40 must disconnect the cross-point because anothercross-point controller is likely to make a conflicting connection basedon another granted reservation.

An alternate method to setting the inhibit lines 80, 82, 88 and 90 willnow be described. This method changes these lines only at the end ofevery cycle of transmissions between the nodes, at which time variousbuffers are checked to determine if sufficient space is available. Thebuffer and combination controller 118 (FIG. 7) checks the fullnessregisters 120a and 120b (FIG. 8) associated with the two output buffers116a and 116b to determine that both buffers have at least two slotsavailable. The controller 118 also checks the fullness register 98associated with the combined request buffer 96 to determine if at leastfour slots are available. The buffer and combination controller 118 thensets the inhibit lines 80 and 82 if either of the two above conditionsis not satisfied or resets them if both conditions are satisfied. Theset or rest condition then continues for the next cycle, at the end ofwhich the testing is repeated.

The buffer and decombination controller 148 checks each fullnessregister associated with each subbuffer of the output buffer 146,assuming the dual sub-buffer implementation of FIG. 8. Each subbuffermust have at least the number of slots available that is the greater of2 or the maximum value length parameter in the list register 100'associated with the combined request buffer 96' (FIGS. 11 and 13). Ifthese conditions are met, the buffer and decombination controller 148resets the inhibit lines 88 and 90. Otherwise they are set active forthe following period.

The previous description relies upon the calculation and transmissionback to the input adaptor of the absolute reservation time V. Analternative approach is to instead calculate at the reservationprocessor 54 the reservation delay before the output adaptor 32 becomesavailable. The delay must be greater than the expected return delay ZKplus possibly an additional delay which accounts for typical blockagetimes. This typical blockage time delay can be tuned for particularsystems. The new reservation delay is used to update a delay clock atthe reservation processor which also decrements to a zero value so as tomaintain a real-time delay indicator. When the reservation delay istransmitted back in the return message S^(R), each node decrements thisdelay according to the time that it has actually delayed the returnmessage, either for blockage delays, for buffering delays, or for normalforwarding delays. Thus when this delay reservation time arrives back atthe input adaptor 30, it indicates the true delay before the controller40 should make the required cross-point connection. Of course, if thereservation delay has been decremented to a negative value, it is toolate to make the connection which must be submitted as another request.Reservation delays in combined returned messages are decombined in thesame ways as were the reservation times V_(i).

The previous description of the switching system of FIG. 3 hadimplicitly assumed that one class of devices attached to the input linesI₀ -I₃ initiated the request for connection through the cross pointswitch 34 to another class of devices connected to the output lines O₀-O₄. The two classes of devices of such an asymmetrical system might beprocessors on the input lines and memories on the output lines. However,many computer systems form symmetrical systems in which any one devicemay request a connection to any other device. Such a system can beeasily attached to the switching system of FIG. 3 by connecting thedevice to both an input line I_(i) and an output line O_(i). Of course,this requires corresponding input and output ports on the attacheddevice. It should be recognized that there then exists two paths throughthe cross-point switch 34 between the two so attached devices D_(i) andD_(j). One path connects I_(i) to O_(j) and another path connects I_(j)to O_(i). According to the invention as described so far, these twocross-point connections are separately set by connection requestappearing on the two input lines I_(i) and I_(j).

For full-duplex communication between the two devices D_(i) and D_(j),it is recommended that each device D_(i) have two input ports I_(i) andI'_(i) to a cross-point switch 150, illustrated in FIG. 14 and similarlyhave two output lines O'_(i) and O_(i) from that switch 150. Afull-duplex path is provided to the device D_(i) by the two lines I_(i)and O'_(i) when the request for connection had been made by that deviceD_(i). However, when the connection request had been made by anotherdevice D_(j), the duplex path to the device D_(i) is provided by thelines I'_(i) and O_(i). A single cross-point controller 40 associatedwith the input line I_(i) controls the cross-point connections for boththe input lines I_(i) and the output lines O'_(i). Obviously, thecross-point connections are between I_(i) and O_(j) and between O'_(i)and I'_(j). It is seen that the horizontal partitioning of thecross-point switch 150 is maintained.

The cross-point switch 150 required for the system of FIG. 14 issomewhat unusual in that some lines are for data transmission in onedirection and other lines are for data transmission in the otherdirection. It may be preferable to divide the cross-point switch 150into two cross-point switches 152 and 154, shown in FIG. 15. A singleset of controllers 40 connected to the adaptors 30 control thecross-point connections on both switches 152 and 154. Each adaptor 30has a source-side line and a destination-side line connected to theDelta network 42. It should be noted, however, that the cross-pointswitch 154 is vertically partitioned rather than horizontallypartitioned, at least within the meaning of that term for FIG. 3 thathorizontally partitioned cross-point arrays have the control linesparallel to the input lines. The advantage of the full-duplex design ofFIG. 15 is that all data flow through the two cross-point switches 152and 154 is unit-directional, thus allowing a simple design for theswitches 152 and 154.

The circuitry of FIG. 15 assumes that the Delta network 42 is two-way,that is, return messages S^(R) are sent back to the source device, D_(i)in the example. If the Delta network 42 is one-way so that no returnmessages are generated and the cross-points are set on the destinationside, then the forward cross-point array 152 would be verticallypartitioned and the reverse array 154 would be horizontally partitioned,with a corresponding change in the control lines from the controllers40.

The switching systems described to this point have required both across-point switch and a separate Delta network. However, it is possibleto use a single cross-point switch for both of the switching functions.The cross-point switch is time-multiplexed so that for a fixed period itis operating as a cross-point swich; but in another fixed period, thecross-point switch is simulating a Delta network. This combination offunctions can be obtained for a type of Delta network known as a perfectshuffle Delta network, an example of which is illustrated in FIG. 16. Inthe illustrated perfect shuffle network, the end stages at a depth d of0 and 2 are composed of 1×2 switching nodes 160 while the middle stageat a depth of 1 is composed of 2×2 switching nodes 162. The importantpoint for the perfect shuffle network is that the connections betweenthe stages are the same regardless of the depth of the network. Forinstance, connections 164a and 116a from a node 160a at d=0 areidentical to connections 164b and 166b from a corresponding node at d=1.Perfect shuffle networks are described in the previously cited technicalarticle by Dias et al. Perfect shuffle networks and their use arefurther described by Stone in a technical article entitled "ParallelProcessing with the Perfect Shuffle" appearing in IEEE Transactions onComputers, Vol. C-20, No. 2, February 1971 at pp. 153-161. A cross-pointswitch can simulate a perfect shuffle network because an adaptorconnected to both an input and an output line from the cross-pointswitch can act as one of the nodes of the perfect shuffle network. Theadaptor, however, is acting as the corresponding nodes for all thedepths of the perfect shuffle network. But because of the constantinterconnection pattern between the stages at the different depths, theswitching is performed the same regardless of the simulated depth.

The use of a cross-point switch for simulating a perfect shuffle networkfor the forward propagation of the control message S^(C) will now bedescribed. The cross-point switch is multiplexed with a period of T. Inthe initial segment of the multiplexing period, data is transmittedthrough the cross-point switch for a period of T-2T_(C). In thissegment, the cross-point switch is being used in its normal fashion forthe selective connection between any of the input and output lines. Thedetermination of the connection is made by the transmission of thecontrol messages S^(C). The multiplexing period is further divided intotwo segments, each of length T_(C). In each of these T_(C) segments,forward control messages S^(C) are transmitted from one adaptor toanother, simulating the perfect shuffle network. For a particularadaptor, the cross-point connection or switching direction for each ofthe two T_(C) periods are respectively the two connections dictated bythe perfect shuffle network. These connections will not vary dependingupon the depth but will vary for which of the four nodes arrangedvertically in FIG. 16 is being simulated by the particular adaptor.

An apparatus for the multiplexed embodiment of the invention is shown inFIG. 18. The cross-point switch 34 can be of the same form as that ofFIG. 3. Associated with each pair of input and output lines I_(i) andO_(i) is a node circuit 170 that includes the previously describedcross-point controller 40 and an I/O adaptor 172. During the multiplexdata period of T-2T_(C), the I/O adaptor 172 acts as the input andoutput adaptors 30 and 32 of FIG. 3. The I/O adaptor 172, during thisperiod, simply connects the input and output lines I"_(i) and O"_(i)from the attached devices to the corresponding input and output linesI_(i) and O_(i) to the cross-point switch 34. During this data period,the controller 40 is making the cross-point connection required for thedata transmission. In the two control message segments T_(C), the I/Oadaptor 172 is possibly receiving control messages S_(C) on the outputline O_(i) and immediately forwards them to an input buffer 174. If onlyone control message is transmitted in each of the segments T_(C), thenthe buffer 174 has a capacity of two messages.

During the following data transmission period of T-2T_(C), the controlmessages in the input buffer 174 are sequentially serviced by areservation and node processor 176. The control message must contain twoadditional parameters, one indicating the depth of the node at which thecontrol message is being received. The control message must also containan indicator as to whether it is forward control message S^(C) or areturn message S^(R). If the depth parameter indicates that the receivedcontrol message is intended for a depth of 2, that is, the right handside of the perfect shuffle network of FIG. 16, then the reservation andnode processor 176 performs similar functions to the reservationprocessor 54 of FIG. 12. Additionally, the reservation and nodeprocessor 176, in this case, must change the depth and directionparameters in the control message period.

However, if the intended depth parameter indicates that furtherswitching is required, such as would be the case with an intended depthof 0 or 1 in FIG. 16 for a forward message S^(C), then the reservationand node processor 176 does not perform the reservation functions uponthe message. Instead, the processor 176 associates with the controlmessage a switching direction dependent upon the intended depthparameter and the address field in the control message. This switchingindicator corresponds to one of the two control segments T_(C) which inturn correspond to the two possible paths from the simulated node. InFIG. 16, the paths 164a and 164b represent one choice and the paths 166aand 166b represent the other choice. This switching indicator is alsoinserted when a control message S^(C) is converted to a return messageS^(R), as described above for the reservation process. All the processedmessages are then stored in a node buffer 178. The node buffer 178 iscontent addressable according to the switching indicator and operates asa first-in/first-out buffer on those messages. In the first controlsegment T_(C), the senior message in the node buffer 178 directed in oneswitching direction is taken from the node buffer 178 and sent to theinput line I_(i). Similarly, during the second control segment T_(C),the senior member in the node buffer 178 directed to the other switchingdirection, is taken from the buffer 178 and put on the input line I_(i).During the two control segments T_(C), the cross-point controller 30 ismaking the connections in the cross-point switch 34 corresponding to thetwo interconnections illustrated for that node in FIG. 16, for example,164a or 164b and 166a or 166b. Thus control messages are beingsimultaneously received and transmitted by the node circuit 170 in eachof the control segments T_(C). Because the node circuit 170 is alsoacting as the entry node, additional messages are transmitted betweenthe device attached to the input and output lines I"_(i) and O"_(i) andthe reservation and node processor 176. A new request for a connectionreceived on the input line I"_(i) is immediately processed by thereservation and node processor 176 to put it in proper form fortransmission to the next simulated node. Similarly, when the reservationand node processor 176 detects that a return message S^(R) has beenreceived at its final destination, that information is given immediatelyto the I/O adaptor 172 for use in a subsequent data transmissionsegment.

It should be noted that the entire path through the perfect shufflenetwork does not need to be simulated if in fact the control messageS^(C) or the return message S^(R) has been received at the node circuit170 which is its final destination.

This shortening of the path through the perfect shuffle network requiresthat the complete addresses be maintained in the address field A.

Although the cross-point switch 34 could be used for the immediatetransmission of the control message across the entire network, there isno guarantee that two such messages would be simultaneously broadcast tothe same destination. This situation is not possible for the timemultiplexing of the two control segments TC of the described method.

The previous description applied to transmission of messages in only onedirection across the perfect shuffle network. In order to use the nodecircuit 170 to simulate the perfect shuffle network in both directions,two additional control segments T_(C) must be included in themultiplexing period. In two of the T_(C) segments, control messagesS_(C) are being forwarded in one direction and in the other two T_(C)segments the return messages are being forwarded in the reversedirection. the cross-point controller 40 and the node buffer 178 mustthen allow for four switching directions and the input buffer 174 mustaccept four messages.

The structure of the Delta control network can be advantageouslycombined with another time multiplexing method to produce a hierarchicalcontrol path. An example of circuitry usable with the hierarchicalmethod is the switching system of FIG. 15. The time sequence is simplyshown in FIG. 19. For a time T-T_(H), the cross-point switch is used fordata transmission. At fixed times, for a period T_(H), the datatransmission is stopped. Any adaptor, which at that time, desires anadditional reservation for a connection, transmits similar connectionrequests S^(C) over both the Delta network and also over the cross-pointswitch. That is, each adaptor ignores possible contention from otheradaptors and causes its controller to make the cross-point connectionfor the control message S_(C), it makes the reservation and returns theconfirmation message S^(R) over the cross-point array to the requestingadaptor.

If a contention situation exists, then two or more adaptors will beattempting to simultaneously send requests S^(C) over the cross-pointarray. Both connections are made and the two messages both becomegarbled. The destination adaptor cannot act on the garbled messages sothat the messages over the cross-point array are ignored. However,similar messages are being transmitted over the Delta network. The Deltanetwork, as previously described, can resolve contention so that bothconflicting control messages will eventually be received over the Deltanetwork. In order to prevent two request messages for the same requestfrom being acted upon, one received over the cross-point array and oneover the Delta network, the two control messages, sent on the differentroutes, each contains a same unique identifier. The destination adaptor,receiving a control message over the Delta network, compares theidentifier with identifiers received over a time representing themaximum delay in the Delta network. Once a source adaptor hastransmitted a request over the cross-point array, it continues totransmit some signal for the duration of the time T_(H). This continuedbroadcasting prevents the successful receipt of two control messages inthe same period T_(H).

This hierarchical process allows for very quick connections to be madeover the cross-pont array in light traffic situations but assures thatthe control message is eventually received over the Delta networkingregardless of traffic conditions.

Having thus described my invention, what I claim as new, and desire tosecure by Letters Patent is:
 1. A method for transmitting data betweensource adaptors and destination adaptors via a cross-point array,comprising the steps of:transmitting data from at least one of saidsource adaptors to a corresponding designated destination adaptor oversaid cross-point array; interrupting said transmitting of data for afirst predetermined time period; transmitting a connection request fromeach of said source adaptors having a connection request over saidcross-point array to a one of said destination adaptors indicated by therespective connections requests without consideration of contention insaid cross-point array with connection requests transmitted over saidcross-point array by other ones of said source adaptors, each of saidconnection requests containing an indentifier indicative of the sourceadaptor from which it is transmitted, said cross-point array being afast but not guaranteed path for said connection requests; returningfrom each destination adaptor receiving an ungarbled connection requestfrom one of said source adaptors over said cross-point array aconfirmation message to the source adaptor which transmitted theconnection request; for each connection request transmitted over saidcross-point array, transmitting a similar connection request over aDelta network, said Delta network being a slower but guaranteed path forsaid connection requests; resolving any contentions between connectionrequests in said Delta network such that each said connection requestwill reach the intended destination adaptor; comparing in eachdestination adaptor receiving a connection request over said Deltanetwork the identifier contained therein with identifiers of anyconnection request received over said cross-point array within apreceding second predetermined time period, within said first timeperiod; and ignoring in each destination adaptor connection requestsreceived over said Delta network having an identifier the same as aconnection request received over said cross-point array within saidsecond time period, whereby, by transmitting said connection requestsover both said cross-point array as a fast but not guaranteed path andover said Delta network as a slower but guaranteed path, an averageresponse time for data transmission approaches a response time attainedif all connection requests were transmitted only over said cross-pointarray with no interference.
 2. The method for transmitting data of claim1, wherein said second predetermined time period is substantially equalto a maximum delay time through said Delta network.
 3. The method fortransmitting data of claim 1, further comprising the step oftransmitting over said cross-point array, from each said source adaptortransmitting a connection request, a signal for any remaining durationof said first time period for preventing receipt of two connectionrequests from the same source adaptor during said first time period. 4.The method for transmitting data of claim 1, wherein said step ofresolving any contentions comprises:storing connection requests in aplurality of respective input buffers; determining which of said inputbuffers has last forwarded a connection request; forwarding theconnection request contained in said input buffer having last forwardeda connection request.
 5. The method for transmitting data of claim 1,wherein said step of resolving any contentions comprises combiningconnection requests from two different source adaptors for the samedestination adaptor into a single message.
 6. The method fortransmitting data of claim 5, wherein said step of combining connectionrequest comprises the steps of:receiving and storing at least tworeservation request, each of said reservation requests including anaddress of a destination adaptor, a requested time of service, and acontrol message; comparing the destination adaptor addresses of each ofsaid reservation request; for at least some of said reservation requestshaving the same destination address, combining said reservation requestsinto a single reservation request including the control messages of thereservation requests being combined and a requested time of serviceequal to the sum of the times of service of the two reservationsrequests being combined.
 7. The method for transmitting data of claim 6,further comprising the step of exempting an oldest reservation requestfrom said step of combining. .Iadd.8. A method of simultaneouslytransmitting addressed messages from a plurality of input adapters to aplurality of addressable output adapters, comprising the stepsof:transmitting addressed messages on a first switching network in whichsaid addressed messages may block each other, so that delivery ofmessages on said first switching network is not guaranteed, but in whicheach message that is delivered is delivered relatively quickly;transmitting at least the addressed messages which are blocked in saidfirst switching network on a seprate second switching network in whichsaid addressed messages cannot block each other, so that delivery ofmessages transmitted on said second switching network is guaranteed, butin which each message transmitted through said second switching networkgets delivered to the addressed output adapter more slowly than on saidfirst switching network; receiving each of said messages which is notblocked in said first switching network at the output adapter addressedby said message; and receiving each of said addressed messages which hasbeen blocked in said first switching network at the output adapteraddressed by said message after it has been transmitted instead throughsaid second swithing network, whereby all of said addressed messages areguaranteed to be delivered to the output adapters addressed by saidmessages and the average delivery time is less than the average deliverytime for messages delivered by said second switching network whichguarantees delivery. .Iaddend. .Iadd.9. Claim 8 wherein said first andsecond switching networks are multi-ported, multi-path switchingnetworks. .Iaddend. .Iadd.10. Claim 9 wherein said first switchingnetwork is a cross-point switch. .Iaddend. .Iadd.11. Claim 9 whereinsaid second switching network is a delta network with buffering..Iaddend. .Iadd.12. Claim 8 wherein said addressed messages aretransmitted on both said first and said second switching networkssimultaneously. .Iaddend. .Iadd.13. Claim 12 wherein an output adapteraddressed by a message receives the same message via both networks inthe event said same message is not blocked in said first switchingnetwork but will respond only to a message received via said secondswitching network when the same message has not been received alreadyvia said first switching network. .Iaddend. .Iadd.14. Apparatus fortransmitting addressed messages among addressable input/output adapters,comprising: a multiplicity of addressable input/output adapters; a firstswitching network interconnecting said input/output adapters fortransmitting addressed messages among said adapters; said firstswitching network being of a type wherein said addressed messages mayblock each other, so that delivery of an addressed message via saidfirst network is not guaranteed, but in which each addressed messagethat is delivered via said first network is delivered relativelyquickly; a second switching network interconnecting said adapters fordelivering at least those addressed messages which are blocked on saidfirst switching network; said second switching network being of a typewherein said addressed messages cannot block each other, so thatdelivery of addressed messages via said second switching network isguaranteed, but in which each addressed message delivered via saidsecond switching network gets delivered more slowly than via said firstswitching network; said adapters receiving via said first switchingnetwork those messages which are not blocked in said first switchingnetwork and and receiving via said second switching network at leastthose messages which are blocked in said first switching network,whereby all of said addressed messages are guaranteed to be delivered tothe adapter addressed by said message and the average delivery time isless than the average delivery time for messages delivered via saidsecond switching network which guarantees delivery. .Iaddend. .Iadd.15.Claim 14 wherein said first and second switching networks aremulti-ported, multi-path switching networks. .Iaddend. .Iadd.16. Claim15 wherein said first switching network is a cross-point switch..Iaddend. .Iadd.17. Claim 15 wherein said second switching network is adelta network with buffering. .Iaddend. .Iadd.18. Claim 14 wherein saidadapters transmit each addressed message simultaneously on said firstand said second switching networks. .Iaddend. .Iadd.19. Claim 18 whereinsaid adapters upon receipt of an addressed message via said firstswitching network ignore the duplicate addressed message received onsaid second switching network. .Iaddend.